1. Field of the Invention
The present invention relates to solid state circuits employing digital logic. More particularly, the present invention relates to dynamic logic circuits employing CMOS field effect transistors.
2. Background of the Invention
In designing complementary metal oxide semiconductor (CMOS) circuits, especially in VLSI applications, the space required for CMOS logic offsets some of the other advantages of CMOS circuitry. This is due to the general requirement in CMOS logic of using equal numbers of n and p channel transistors in designing ratioless CMOS logic gates. In general an N input logic gate implemented in CMOS will have 2N transistors, N p type and N n type transistors. This results in considerable extra area required in the chip. Ratioed CMOS logic only requires N+1 transistors, typically N n type and one p type, but power is consumed even when the logic circuit is not switching. One technique which has been used to relax this requirement and reduce chip size utilizes a clock to control the operation of the logic gates. Such clocked logic is referred to as dynamic logic. Dynamic logic is described, for example, in William M. Penney, Lillian Lau, eds., MOS Integrated Circuits, Van Nostrand & Co. (1972), pp. 260-288.
In dynamic logic the logic gates are precharged to a predetermined voltage level during one phase of a clock signal and then during a separate "evaluation" clock phase the logic outputs of the gates are determined or evaluated from the logic inputs. The capacitive storage of charge in the transistors allows the retention of information between the precharge and evaluation clock phases. Since there is no continuous current flow in dynamic logic CMOS circuits, power dissipation is at a much lower level than would otherwise be the case in static ratioed CMOS design. Also, the general static CMOS requirement of equal numbers of n and p type transistors may be relaxed reducing the number of transistors per logic gate and reducing chip area.
One example of a complex circuit where dynamic logic has been employed is the programmable logic array (PLA). Programmable logic arrays are a well-known method of implementing logic in complex digital circuits. Programmable logic arrays typically have a two "plane" structure, i.e. two separate regions or groupings of logic gates with the outputs from one region leading into the other. For example, a typical PLA comprises a plane of AND gates which leads into a plane of OR gates. Equivalently, the AND and OR planes may be implemented using NAND gates and inverters in one plane and NOR gates and inverters in the other plane. This type of two-plane PLA allows a large number of arbitrary logic equations to be implemented in an orderly manner. The orderly structure of PLAs is particularly advantageous in designing large scale integrated (LSI) or very large scale integrated (VLSI) systems.
The programming of a PLA may be achieved in several different ways. For example, in mask-programmable PLAs the logic array may be built up on an integrated circuit chip using several masks in the formation of the chip. The final logic connections are left to one or two mask steps which can be relatively easily modified. Other more flexible systems, sometimes referred to as field programmable PLAs, use fuses which can be blown or electrically programmable transistors to allow programming after chip manufacture.
A drawback of dynamic logic, especially in complex circuits, such as PLAs, is that correctly synchronizing the precharge and evaluation functions of a dynamic CMOS circuit can raise difficult timing and design problems. One type of timing problem which can arise in dynamic CMOS logic circuits is the so-called clock race problem which arises due to overlap of clock phases since ideally synchronized square-wave clock signals are not possible in practice. One approach to avoiding such clock race conditions is the NORA (NO RAce), or n-p CMOS, dynamic logic technique. Nelson F. Goncalves, Hugo J. DeMan, NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures, IEEE J. Solid-State Circuits, Vol. SC-18, No. 3 (June 1983).
This CMOS dynamic logic technique does not ensure absence of other types of race problems in the circuit, however. Also, other design problems, such as charge sharing, may be present in complex dynamic CMOS circuits. These disadvantages are discussed, e.g. in David J. Myers, Peter A. Ivey, A Design Style for VLSI CMOS, IEEE J. Solid-State Circuits, Vol. SC-20, No. 3 (June 1985). That article advocates the use of a four clock phase dynamic logic design. Other four clock logic approaches have also been employed. E.g., Neil Weste, Camran Eshraghin, Principles of CMOS VLSI Design, Addison Wesley (1985), p. 215. The use of four clock signals, however, has disadvantages in terms of added clock lines and complicated circuit layout, especially in VLSI circuits.